In a semiconductor memory device in which memory cells are three-dimensionally arranged, such as a three-dimensional NAND type flash memory device, multiple word lines are stacked on a substrate and semiconductor pillars penetrating the ward line. Memory cells are formed at intersections of the semiconductor pillar and the word lines. For an increased memory capacity in a semiconductor memory device having such a structure, it is effective to increase a density of semiconductor pillars and increase a number of stacked word lines. However, in a memory cell array including densely packed word lines and miniaturized semiconductor pillars, there is a high possibility that structural defects may occur as the number of stacked word lines increases.